Journal Papers


    1. Kwang-Jow Gan*,Chun-I Guo, Ping-Feng Wu, and Yaw-Hwang Chen, “Design and Analysis of the Dynamic Frequency Divider Using the BiCMOS-NDR Chaos-Based Circuit”,revised by  Analog Integrated Circuits and Signal Processing,2016.
    2. Kwang-Jow Gan*,Jian-Syong Huang, Wen-Kuan Yeh, Chun-Yi Guo, and Jeng-Jong Lu, “Design of Multi-Threshold Threshold Gate Using MOS-NDR Circuits Suitable for CMOS Process”,revised by  Analog Integrated Circuits and Signal Processing,2016.
    3. Wen-Kuan Yeh, Wenqi Zhang, Yi-Lin Yang, An-Ni Dai, Kehuey Wu, Tung-Huan Chou, Cheng-Li Lin, Kwang-Jow Gan,Chia-Hung Shih and Po-Ying Chen, “The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET”,IEEE Transactions on Device and Materials Reliability,Volume: 16, Issue: 4, pp. 610-616,2016.
    4. Kwang-Jow Gan*,Jeng-Jong Lu, Wen-Kuan Yeh, Yaw-Hwang Chen, and Yan-Wun Chen, “Multiple-Valued Logic Design Based on the Multiple-Peak BiCMOS-NDR Circuits”,Engineering Science and Technology,an International Journal,Volume 19, Issue 2, pp. 888-893, June, 2016.
    5. Kwang-Jow Gan*,Zheng-Jie Jiang, Yaw-Hwang Chen, and Wen-Kuan Yeh, “Application of NDR-Based Van Der Pol Oscillator Based on BiCMOS Technology”,Far East Journal of Electronics and Communications,Vol.16(1), pp. 189-198, March, 2016.
    6. Kwang-Jow Gan*,Ping-Feng Wu, Wen-Kuan Yeh, Jeng-Jong Lu, and Yaw-Hwang Chen, “Design of the Dynamic Frequency Divider Using the BiCMOS-NDR Chaos-Based Circuit”,submitted to  International Journal of Electronics and Communications,2015.
    7. Kwang-Jow Gan*,Chun-Yi Guo, Wen-Kuan Yeh, and Yaw-Hwang Chen, “Design of MOBILE-based Logic Gate Using MOS-NDR Circuits Under 1 V Bias”,revised by  Active and Passive Electronic Components,2015.
    8. Kwang-Jow Gan*,Kuan-Yu Chun, Wen-Kuan Yeh, Yaw-Hwang Chen, Wein-So Wang, “Design of Dynamic Frequency Divider Using Negative Differential Resistance Circuit”,International Journal on Recent and Innovation Trends in Computing and Communication(IJRITCC),Volume 3, Issue 8, pp. 5224-5228, Aug 15, 2015. (ISSN: 2321-8169).
    9. J.J. Lu, K.J. Gan,T.S. Mo, and T.C. Lin, “Observation of the quantum critical behavior in the evolution from spin-glass to intermediate-valence behavior in Ce2Cu1-xCoxSi3 series,” Journal of Superconductivity and Novel Magnetism,Vol. 26, No. 6, pp. 2175-2179, June, 2013. (ISSN : 1557-1939) (SCI)
    10. Kwang-Jow Gan*,Zhen-Kai Kao, Cher-Shiung Tsai, Din-Yuen Chan, and Jian-Syong Huang, “Logic Circuit Design Based on Series-Connected CMOS-NDR Circuit”,International Journal of Computer Theory and Engineering,Vol. 5, No. 3, pp. 562-566, June 2013. (EI) (ISSN : 1793-8201)
    11. Kwang-Jow Gan*, Zheng-Jie Jiang, Cher-Shiung Tsai, Din-Yuen Chan, Jian-Syong Huang, Zhen-Kai Kao, and Wen-Kuan Yeh, “Design of NDR-Based Oscillators Suitable for the Nano-Based BiCMOS Technique”,Applied Mechanics and Materials,Vol. 328, pp 669-673,2013. (SCOPUS, EI Compendex) (ISSN: 1660-9336)
    12. Wen-Kuan Yeh,Po-Ying Chen,Kwang-Jow Gan, Jer-Chyi Wang, and Chao-Sung Lai, “The Impact of Interface/Border Defect on Performance and Reliability of High-k/Metal-Gate CMOSFET”,Microelectronics Reliability,Vol. 53, pp. 265-269, February, 2013.(ISSN : 0026-2714) (SCI)
    13. Cher-Shiung Tsai, Kwang-Jow Gan*, and Ming-Shin Lin,“Low Phase Noise and Wide Tuning Range VCO Using the MOS Differential Amplifier with Active Load”,Circuits and Systems,Vol. 3, No. 4, pp. 307-310, October, 2012.(ISSN:2153-1285)
    14. Kwang-Jow Gan*, Cher-Shiung Tsai, and Shih-Hao Liu, “Multiple-Input Logic Circuit Design Using BiCMOS-Based Negative Differential Resistance Circuits”, Analog Integrated Circuits and Signal Processing, Vol. 73, No. 1, pp. 409-414, October, 2012. (ISSN:0925-1030) (SCI).
    15. Kwang-Jow Gan*, Cher-Shiung Tsai, and Shih-Hao Liu, “Multiple-Input Logic Circuit Design Using BiCMOS-Based Negative Differential Resistance Circuits”, accepted by Analog Integrated Circuits and Signal Processing. July, 2011.
    16. Chih-Lung Lin, Chun-Da Tu, Cha-En. Wu, Chia-Che Hung, Kwang-Jow Gan, and Kuan-Wen Chou, “Low Power Gate Driver Circuit for TFT-LCD Application,” IEEE Trans. Electron Devices, Vol. 59, No. 5, pp. 1410-1415, May, 2012.
    17. Kwang-Jow Gan*, Cher-Shiung Tsai, Kuan-Yu Chun, Wen-Kuan Yeh, and Jeng-Jong Lu, “Frequency Divider Design Using the Combination of Transistors and Passive Devices”, Analog Integrated Circuits and Signal Processing, Vol. 70, Iss. 1, pp. 141-145, January, 2012. (ISSN:0925-1030) (SCI)
    18. Kwang-Jow Gan*, Cher-Shiung Tsai, Chi-Wen Hsien, Yu-Kuang Li, and Wen-Kuan Yeh, “Design of Monostable-Bistable Transition Logic Element Using the BiCMOS-Based Negative Differential Resistance Circuit”, Analog Integrated Circuits and Signal Processing, Vol. 68, No. 3, pp. 379-385, September, 2011. (ISSN:0925-1030) (SCI) IF=0.452
    19. J. J. Lu, T. S. Mo, K. J. Gan, J. F. Chou, M. K. Lee, “Magnetic anomalies and spin-glass-like behavior in Ce2CuGe6”, Journal of Superconductivity and Novel Magnetism, Vol. 24, No. 6, pp. 1991-1995, August, 2011. IF=1.204 (ISSN:0304-8853) (SCI)
    20. Bing-Jing Li, Chih-Hsiang Chang, Yun-Kuin Su, and Kwang-Jow Gan, “Thermal Dissipation of High-Brightness Light Emitting Diode by Using Multi-walled Carbon Nanotube/SiC Composites”, Japanese Journal of Applied Physics, Vol. 50, Iss. 6, pp. 06GE09-06GE09-4, June, 2011. (ISSN: 0021-4922) (SCI) IF=1.018
    21. Wen-Kuan Yeh, Yu-Ting Chen, Fon-Shan Huang, Chia-Wei Hsu, Chun-Yu Chen, Yean-Kuen Fang, Kwang-Jow Gan, and Po-Ying Chen, “The Improvement of High-k/Metal Gate pMOSFET Performance and Reliability Using Optimism Si Cap/SiGe Channel Structure”, IEEE Transactions on Device and Materials Reliability, Vol. 11, No. 1, pp. 7-12, March, 2011. (ISSN: 1530-4388) (SCI) IF=1.95
    22. J. J. Lu, T. C. Lin, S. Y. Tsai, T. S. Mo, K. J. Gan, “Structural, magnetic and transport properties of Ni-doped ZnO films”, Journal of Magnetism and Magnetic Materials, Vol. 323, Iss. 6, pp. 829-832, March, 2011. IF=1.204 (ISSN:0304-8853) (SCI)
    23. Kwang-Jow Gan*, Cher-Shiung Tsai, Yu-Kuang Li, and Jeng-Jong Lu, “Logic Circuit Design Using Monostable-Bistable Transition Logic Element Based on Standard BiCMOS Process”, Microelectronics Journal, Vol. 42, No. 2, pp. 477-482, February, 2011. (ISSN:0026-2692) (SCI) IF=0.787.
    24. Kwang-Jow Gan*, Cher-Shiung Tsai, Yan-Wun Chen, and Wen-Kuan Yeh, “Voltage-Controlled Multiple-Valued Logic Design Using Negative Differential Resistance Devices”, Solid-State Electronics, Vol. 54, Iss. 12, pp. 1637-1640, December, 2010. (ISSN:0038-1101) (SCI) IF=1.494, Ranking:73/246
    25. J. J. Lu, T. S. Mo, K. J. Gan, T. C. Lin, and M. K. Lee, “Observation of RKKY-Kondo Competition and Non-Fermi-Liquid Behavior in the Intermetallic Compound Series Ce(Cu1-xNix)Si2”, Journal of Superconductivity and Novel Magnetism, Vol. 23, Iss. 8, pp. 1473-1477, June, 2010. (ISSN: 1557-1939) (SCI)
    26. Kwang-Jow Gan*, Dong-Shong Liang, and Yan-Wun Chen, “Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources”, IEICE Transactions on Information & Systems, Special Section on Multiple-Valued Logic and VLSI Computing, Vol. E93-D, No.8, pp. 2068-2072, August, 2010. (ISSN: 0916-8532) (SCI)
    27. Kwang-Jow Gan*, and Dong-Shong Liang, “Investigation of Adjustable Current-Voltage Characteristics and Hysteresis Phenomena for Multiple-Peak Negative Differential Resistance Circuit,” IEICE Transactions on Electronics, Vol. E93-C  No.4, pp.514-520, April, 2010. (ISSN: 0916-8524) (SCI)
    28. Kwang-Jow Gan*, Cher-Shiung Tsai, and Dong-Shong Liang, “Design and Characterization of the Negative Differential Resistance Circuits Using the CMOS and BiCMOS Process,” Analog Integrated Circuits and Signal Processing, Vol. 62, No. 1, pp. 63-68, January, 2010. (ISSN:0925-1030) (SCI)
    29. J. J. Lu, S. Y. Tsai, Y. M. Lu, T. C. Lin, and K. J. Gan, “Al-doping effect on structural, transport and optical properties of ZnO films by simultaneous RF and DC magnetron sputtering,” Solid State Communications, Vol. 149, Iss. 47-48, pp. 2177-2180, December, 2009. (ISSN: 0038-1098) (SCI)
    30. Dong-Shong Liang, Kwang-Jow Gan*, Cheng-Chi Tai, and Cher-Shiung Tsai, "Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio," IEICE Transactions on Electronics, Vol. E92-C, No. 5, pp. 635-638, May, 2009. (SCI) (ISSN: 0916-8524)
    31. Kwang-Jow Gan*, Dong-Shong Liang, and Cher-Shiung Tsai, “Novel Multiple-Selected and Multiple-Valued Memory Design Using Negative Differential Resistance Circuits Suitable for Standard SiGe-Based BiCMOS Process,” Analog Integrated Circuits and Signal Processing, Vol. 59, Issue 2, pp. 161-167, May, 2009. (ISSN:0925-1030) (SCI)
    32. Kwang-Jow Gan*, Dong-Shong Liang, Cher-Shiung Tsai, Chun-Ming Wen, and Yaw-Hwang Chen, “Design and Fabrication of Multiple-Valued Multiplexer Using Negative Differential Resistance Circuits and Standard SiGe Process,” Solid-State Electronics, Vol. 52, No. 6, pp. 882-885, June, 2008. (ISSN:0038-1101) (SCI)
    33. Kwang-Jow Gan*, Cher-Shiung Tsai, Dong-Shong Liang, Chun-Da Tu, and Yaw-Hwang Chen, “Multiple-Input NOR Logic Design Using Negative Differential Resistance Circuits Implemented by Standard SiGe Process,” Solid-State Electronics, Vol. 52, Iss. 2, pp. 175-178, February, 2008. (ISSN:0038-1101) (SCI)
    34. Kwang-Jow Gan*, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen and Chun-Ming Wen, “Multiple-Valued Decoder Using MOS-HBT-NDR Circuit,” Electronics Letters, Vol. 43, No. 20, pp. 1092-1093, September, 2007. (ISSN: 0013-5194) (SCI)
    35. Kwang-Jow Gan*, Cher-Shiung Tsai, and Wei-Lun Sun, “Fabrication and Application of MOS-HBT-NDR Circuit Using Standard SiGe Process,” Electronics Letters, Vol. 43, No. 9, pp. 516-517, April, 2007. (ISSN: 0013-5194) (SCI)
    36. Kwang-Jow Gan*, Cher-Shiung Tsai, Dong-Shong Liang, Chun-Ming Wen, and Yaw-Hwang Chen, “Tri-Valued Memory Circuit Using MOS-BJT-NDR Circuits Fabricated by Standard SiGe Process,” Japanese Journal of Applied Physics, Vol. 45, No. 46, pp. L977-979, 2006. (ISSN: 0021-4922) (SCI)
    37. Kwang-Jow Gan*, Yaw-Hwang Chen, Cher-Shiung Tsai, and Long-Xian Su, “Four-Valued Memory Circuit Using Three-Peak MOS-NDR Devices and Circuits,” Electronics Letters, Vol. 42, Iss. 9, pp. 514-515, 2006. (SCI) (ISSN: 0013-5194) (SCI)
    38. Kwang-Jow Gan*,“Investigation of the Combined Current-Voltage Characteristics of Two Similar Esaki-Diode-Like Devices,”Japanese Journal of Applied Physics, Vol. 42, No. 10, pp. 6354-6358, 2003. (SCI)
    39. Kwang-Jow Gan*“Characterization of the extrinsic hysteresis phenomena of series-connected identical Esaki-diode-like NDR devices,”Japanese Journal of Applied Physics, Vol. 41, No. 3A, pp. 1293-1299, 2002. (SCI)
    40. Kwang-Jow Gan*“The low-high-low I-V characteristics of five to seven peaks based on four NDR devices,”IEEE Transactions on Electron Devices, Vol. 48, No. 8, pp. 1683-1687, 2001. (SCI)
    41. Kwang-Jow Gan*“Hysteresis phenomena for the series circuit of two identical negative differential resistance devices,”Japanese Journal of Applied Physics, Vol. 40, No. 4A, pp. 2159-2164, 2001. (SCI)
    42. Kwang-Jow Gan*“Novel four-peak or five-peak current-voltage characteristics for three negative differential resistance devices in series,”Solid-State Electronics, Vol. 44, pp. 1597-1602, 2000. (SCI)
    43. Kwang-Jow Gan* and Yan-Kuin Su,“Novel multipeak current-voltage characteristic of series-connected negative differential resistance devices,”IEEE Electron Device Letters, Vol. 19, No. 4, pp. 109-111, 1998. (SCI)
    44. Kwang-Jow Gan*, Yan-Kuin Su and Ruey-Lue Wang,“Simulation and analysis of negative differential resistance devices and circuits by load-line method and Pspice,”Solid State Electronics, Vol. 42, No. 1, pp. 176-180, 1998. (SCI)
    45. Kwang-Jow Gan* and Yan-Kuin Su,“Modeling current-voltage and hysteretic current-voltage characteristics with two resonant tunneling diodes connected in series,”Solid-State Electronics, Vol. 41, No. 12, pp. 1917-1922, 1997. (SCI)
    46. Kwang-Jow Gan* and Yan-Kuin Su,“Modeling multipeak current-voltage characteristic and hysteresis phenomena for several resonant tunneling diodes connected in series,”Journal of Applied Physics, Vol. 82, No. 11, pp. 5822-5828, 1997. (SCI)
    47. Kwang-Jow Gan* and Yan-Kuin Su,“Improved circuit design of multipeak current-voltage characteristics based on resonant tunneling diodes,”Japanese Journal of Applied Physics, Vol. 36, No. 10, p p. 6280-6284, 1997. (SCI)
    48. Kwang-Jow Gan*, Yan-Kuin Su and Ruey-Lue Wang,“Modeling of three-peak current-voltage vharacteristics with two resonant tunneling diodes connected in series,”Journal of Applied Physics, Vol. 81, No. 10, pp. 6825-6829, 1997. (SCI)
    49. Y. K. Su, F. S. Juang, N. Y. Li, K. J. Gan and T. S. Wu,“Heteroepitaxial growth of gallium antimonide on GaAs by low pressure MOVPE,”Solid-State Electronics, Vol. 34, No. 8, pp. 815-819, 1991. (SCI)
    50. Y. K. Su, K. J. Gan*, F. S. Juang and J. S. Hwang,“Characterization of Si-implanted gallium antimonide,”Nuclear Instruments and Methods in Physics Research, B55, pp. 794-797, 1991. (SCI)
    51. Y. K. Su, F. S. Juang, and K. J. Gan,“Ohmic contacts of AuGeNi and Ag/AuGeNi to n-GaSb with various sintering temperature,”Japanese Journal of Applied Physics, Vol. 30, No. 5, pp.914-916, 1991. (SCI)
    52. Y. K. Su and K. J. Gan*,“Raman spectra of Si-implanted GaSb,”Journal of Applied Physics, Vol. 68, No. 11, pp.5584-5587, 1990. (SCI)
    53. F. S. Juang, Y. K. Su, N. Y. Li, and K. J. Gan,“Effects of TMSb/TEGa ratios on epilayer properties of GaSb grown by low pressure MOCVD,”Journal of Applied Physics, Vol. 68, No. 12, pp.6383-6387, 1990. (SCI)



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